Turning to FIG. 1A, a conventional ADC system 100 can be seen. In operation, the clock buffer 102 buffers a clock signal CLK, which is provided to DLL 104 and delay circuit 106. Delay 106 provides a sample signal SP to a sampling circuit (which is generally comprised of sampling switch SS and sampling capacitor CS) so that the sampling circuit can sample the analog input signal AIN. The DLL 104 (which is generally comprised of phase detector (PD) 116, charge pump 118, loop filter 120, and delay line 112) generates output signals from taps within delay line 112. Specifically, the delay line 112 is fully variable, having a set of buffers 114-1 to 114-N that are coupled in series with one another and controlled by the output signal from loop filter 120. From these output signals from the taps associated with buffers 114-1 to 114-N, clock generator 108 is able to generate clock signals for ADC 110 that each correspond to one of the taps from the delay line 112, with the first clock signal EDGE1 operating as the hold signal HOLD for ADC.
In FIGS. 1B and 1C, a timing diagram for system 100 can be seen. When the sample signal SP is logic high, the sample switch SS and the sample capacitor CS samples the analog input signal AIN. If the delay circuit 106 were removed from system 100 (which is assumed for FIG. 1B), the rising edge of signal EDGE1 from buffer 114-1 would lag the falling edge of the sampling signal SP, and the rising edge of hold signal HOLD output from clock generator 108 would lag the rising edge of signal EDGE1. With the delay circuit 106 in place (which is assumed for FIG. 1C), the falling edge of sample signal SP and the rising edge of signal EDGE1, yet the hold signal HOLD continues to lag signal EDGE1. Thus, it is desirable to include this delay to obtain the edge alignment, yet it also is desirable to eliminate delay circuit 106 to reduce jitter.
Since DLL 104 locks to the full period of clock signal CLK, one could potentially use phases generated at the end of delay line 112. In FIG. 1D, signal EDGE(N−1) from buffer 114-(N−1) is used as the hold signal HOLD. However, this technique is generally limited to a particular clock speed. At lower speeds (as shown in FIG. 1E), the delay for signal EDGE(N−1) changes but the delay difference between sampling clock SP and other logic delays for ADC do not change. Thus, the rising edge of signal EDGE(N−1) (after additional delay) occurs before the falling edge of the sampling clock SP and hold signal HOLD occurs before sampling clock, resulting in a functional failure. Essentially, because DLL 104 has N phases from the taps associated with buffers 114-1 to 114-N that are each separated by a delay of TCLK/N (where TCLK is period of clock signal CLK), the delay between the sampling clock SP and signal EDGE(N−1) is dependant on clock frequency TCLK so that the rising edge of signal EDGE(N−1) used for hold signal HOLD can occur prior to a falling edge of the sampling clock SP when the speed of clock signal CLK is reduced.
Some other conventional systems are: U.S. Pat. Nos. 6,867,627; 7,161,402; and 7,325,175.